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» Quasi-Resonant Interconnects: A Low Power Design Methodology
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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 8 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
SLIP
2004
ACM
14 years 1 months ago
Optical solutions for system-level interconnect
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
Ian O'Connor
HOTI
2008
IEEE
14 years 2 months ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
14 years 1 months ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh
ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
14 years 1 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif