214 search results - page 31 / 43 » Quasi-Resonant Interconnects: A Low Power Design Methodology |
DAC
2005
ACM
13 years 10 months ago
2005
ACM
Methodology, EDA Flow, scripts, and documentation plays a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on l...
DAC
1998
ACM
14 years 9 months ago
1998
ACM
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...
JSA
2010
13 years 2 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
CDC
2010
IEEE
13 years 2 months ago
2010
IEEE
This paper deals with hierarchical model predictive control (MPC) of distributed systems. A threelevel hierarchical approach is proposed, consisting of a high level MPC controller,...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...