5762 search results - page 1118 / 1153 » R-tree: A Hardware Implementation |
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
HPCS
2005
IEEE
14 years 2 months ago
2005
IEEE
Abstract— In recent years our society has witnessed an unprecedented growth in computing power available to tackle important problems in science, engineering and medicine. For ex...
IOLTS
2005
IEEE
14 years 2 months ago
2005
IEEE
— In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in G...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...