5762 search results - page 91 / 1153 » R-tree: A Hardware Implementation |
160
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ISSS
2002
IEEE
15 years 9 months ago
2002
IEEE
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
135
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CODES
2004
IEEE
15 years 8 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
131
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DATE
2008
IEEE
15 years 11 months ago
2008
IEEE
In the field of the Side Channel Analysis, hardware distortions such as glitches and random frequency are classical countermeasures. A glitch influences the side channel amplitu...
112
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DATE
2007
IEEE
15 years 11 months ago
2007
IEEE
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
117
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DATE
2007
IEEE
15 years 11 months ago
2007
IEEE
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...