211 search results - page 28 / 43 » REDEFIS: a system with a redefinable instruction set process... |
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
ASPLOS
2000
ACM
14 years 1 hour ago
2000
ACM
This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years,...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
ISCA
2000
IEEE
14 years 15 hour ago
2000
IEEE
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
SIGOPS
2011
13 years 2 months ago
2011
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...