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DAC
2004
ACM
14 years 3 months ago
A timing-driven module-based chip design flow
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
Fan Mo, Robert K. Brayton
VLSID
2003
IEEE
104views VLSI» more  VLSID 2003»
14 years 3 months ago
Interfacing Cores with On-chip Packet-Switched Networks
With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the ...
Praveen Bhojwani, Rabi N. Mahapatra
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 2 months ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
AGILEDC
2009
IEEE
14 years 2 months ago
Scrum and CMMI
Projects combining agile methods with CMMI1 are more successful in producing higher quality software that more effectively meets customer needs at a faster pace. Systematic Softwa...
Carsten Ruseng Jakobsen, Jeff Sutherland
DEXAW
2002
IEEE
127views Database» more  DEXAW 2002»
14 years 2 months ago
Enhanced Multi-Version Data Broadcast Schemes for Time-Constrained Mobile Computing Systems
In this paper, we study the data dissemination problem in time-constrained mobile computing systems (TCMCS) in which maximizing data currency (minimizing staleness) and meeting tr...
Hei-Wing Leung, Joe Chun-Hung Yuen, Kam-yiu Lam, E...