375 search results - page 7 / 75 » RTL power estimation and optimization |
ARITH
2009
IEEE
14 years 3 months ago
2009
IEEE
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
DATE
2004
IEEE
14 years 11 days ago
2004
IEEE
This paper presents a versatile hardware/software cosimulation and co-design environment for embedded 3D graphics accelerators. The GRAphics AcceLerator design exploration framewo...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
DATE
1999
IEEE
14 years 28 days ago
1999
IEEE
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...