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FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
14 years 5 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
IEEEPACT
2008
IEEE
14 years 5 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
ISCAS
2006
IEEE
133views Hardware» more  ISCAS 2006»
14 years 5 months ago
A psychiatric patients tracking system
This paper presents an RFID based psychiatric critical to psychiatric patient treatment. The work oftracking patient tracking system in a psychiatric patient care center. In psychi...
Ming-Hua Tsai, Chieh-Ling Huang, Pau-Choo Chung, Y...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 9 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 9 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt