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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
14 years 23 days ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
VTS
2002
IEEE
126views Hardware» more  VTS 2002»
14 years 11 days ago
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
14 years 13 days ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
AINA
2006
IEEE
14 years 1 months ago
Collaborative Fault Diagnosis in Grids through Automated Tests
Grids have the potential to revolutionize computing by providing ubiquitous, on demand access to computational services and resources. However, grid systems are extremely large, c...
Alexandre Duarte, Francisco Vilar Brasileiro, Walf...
AIIDE
2009
13 years 8 months ago
Computational Support for Play Testing Game Sketches
Early-stage game prototypes need to be informative without requiring excessive commitments. Paper prototypes are frequently used as a way of trying out core mechanics while leavin...
Adam M. Smith, Mark J. Nelson, Michael Mateas