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1998
Tsinghua U.
13 years 11 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
DATE
2009
IEEE
97views Hardware» more  DATE 2009»
14 years 2 months ago
A flexible floating-point wavelet transform and wavelet packet processor
—The richness of wavelet transformation is known in many fields. There exist different classes of wavelet filters that can be used depending on the application. In this paper, ...
Andre Guntoro, Manfred Glesner
ECRTS
2009
IEEE
13 years 5 months ago
Using Randomized Caches in Probabilistic Real-Time Systems
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access p...
Eduardo Quiñones, Emery D. Berger, Guillem ...
ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
14 years 1 months ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
13 years 12 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi