193 search results - page 13 / 39 » Reasoning about Memory Layouts |
ICS
2001
Tsinghua U.
14 years 2 months ago
2001
Tsinghua U.
Application performance tuning is a complex process that requires assembling various types of information and correlating it with source code to pinpoint the causes of performance...
DDECS
2009
IEEE
14 years 1 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
CHI
2010
ACM
14 years 4 months ago
2010
ACM
Network visualisations use clustering approaches to simplify the presentation of complex graph structures. We present a novel application of clustering algorithms, which controls ...
MICRO
2002
IEEE
14 years 2 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
HASKELL
2009
ACM
14 years 4 months ago
2009
ACM
We address the problem of reasoning about Haskell programs that use Software Transactional Memory (STM). As a motivating example, we consider Haskell code for a concurrent non-det...