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» Reclocking for high-level synthesis

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DAC
1989
ACM

181views Computer Architecture» more DAC 1989»

Scheduling and Binding Algorithms for High-Level Synthesis

13 years 11 months ago

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- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...

Pierre G. Paulin, John P. Knight

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ASAP
2007
IEEE

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Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis

13 years 9 months ago

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In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...

Alain Darte, C. Quinson

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VTS
1999
IEEE

106views Hardware» more VTS 1999»

RT-level TPG Exploiting High-Level Synthesis Information

13 years 11 months ago

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High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...

Silvia Chiusano, Fulvio Corno, Paolo Prinetto

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ISSS
1996
IEEE

73views Hardware» more ISSS 1996»

Layout-Driven RTL Binding Techniques for High-Level Synthesis

13 years 11 months ago