174 search results - page 29 / 35 » Reclocking for high-level synthesis |
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
FM
1999
Springer
13 years 11 months ago
1999
Springer
ÐIn this paper, we describe the incremental specification of a power transformer station controller using a controller synthesis methodology. We specify the main requirements as s...
ASAP
1996
IEEE
13 years 11 months ago
1996
IEEE
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
ISSS
1997
IEEE
13 years 11 months ago
1997
IEEE
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases . There exists some tools that give an o...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...