174 search results - page 30 / 35 » Reclocking for high-level synthesis |
CORR
2006
Springer
13 years 7 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
ISSS
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper we discuss, what breakpoints in Source Level Emulationa are, how we can work with them and how we have to change the cicuit generated by high level synthesis to do s...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
As device feature size decreases, interconnection delay becomes the dominating factor of system performance. Thus it is important that accurate physical information is used during...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
CCL
1994
Springer
13 years 11 months ago
1994
Springer
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...