68 search results - page 2 / 14 » Reconfigurable Processing Units vs. Reconfigurable Interconn... |
VLSID
2002
IEEE
14 years 11 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
ERSA
2009
13 years 8 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
PARELEC
2000
IEEE
14 years 3 months ago
2000
IEEE
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
FCCM
1999
IEEE
14 years 3 months ago
1999
IEEE
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
FPL
2008
Springer
14 years 12 days ago
2008
Springer
Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of de...