55 search results - page 4 / 11 » Reconfigurable scan chains: a novel approach to reduce test ... |
DATE
2003
IEEE
14 years 21 days ago
2003
IEEE
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
DFT
2002
IEEE
14 years 11 days ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
DAC
2003
ACM
14 years 20 days ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
ET
2002
13 years 7 months ago
2002
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...