30 search results - page 2 / 6 » Reduced Delay BCD Adder |
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
ICCAD
2000
IEEE
14 years 1 days ago
2000
IEEE
—As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the co...
IWANN
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low pow...
ICC
2011
IEEE
12 years 7 months ago
2011
IEEE
—This paper presents an approach to implement a high-performance 8-tap digital FIR (Finite Impulse Response) filter using the Logarithmic Number System. In the past, FIR filter...