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» Reducibility and TT-Lifting for Computation Types
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HIPEAC
2007
Springer
14 years 2 months ago
Fetch Gating Control Through Speculative Instruction Window Weighting
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
Hans Vandierendonck, André Seznec
ASPLOS
2006
ACM
14 years 2 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
CODES
2005
IEEE
14 years 2 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
INFOVIS
2005
IEEE
14 years 2 months ago
PRISAD: A Partitioned Rendering Infrastructure for Scalable Accordion Drawing
We present PRISAD, the first generic rendering infrastructure for information visualization applications that use the accordion drawing technique: rubber-sheet navigation with gu...
James Slack, Kristian Hildebrand, Tamara Munzner
SOUPS
2005
ACM
14 years 2 months ago
Authentication using graphical passwords: effects of tolerance and image choice
Graphical passwords are an alternative to alphanumeric passwords in which users click on images to authenticate themselves rather than type alphanumeric strings. We have developed...
Susan Wiedenbeck, Jim Waters, Jean-Camille Birget,...