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» Reducing Branch Costs via Branch Alignment
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IEEEPACT
2006
IEEE
14 years 1 months ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
14 years 1 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
TWC
2010
13 years 2 months ago
Reducing Call Routing Cost for Femtocells
Femtocell is an effective solution to improve indoor coverage for cellular networks, where short-range and low-power Base Stations (BSs) called Femto BSs are deployed in small area...
Yi-Bing Lin, Chai-Hien Gan, Ching-Feng Liang
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
13 years 11 months ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee
BMCBI
2008
93views more  BMCBI 2008»
13 years 7 months ago
SlowFaster, a user-friendly program for slow-fast analysis and its application on phylogeny of Blastocystis
Background: Slow-fast analysis is a simple and effective method to reduce the influence of substitution saturation, one of the causes of phylogenetic noise and long branch attract...
Martin Kostka, Magdalena Uzlikova, Ivan Cepicka, J...