663 search results - page 56 / 133 » Reducing Compilation Time Overhead in Compiled Simulators |
ISCAPDCS
2007
13 years 9 months ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
DAGSTUHL
2006
13 years 9 months ago
2006
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
CAINE
2006
13 years 9 months ago
2006
The synergy of software and hardware leads to efficient application expression profile (AEP) not only in terms of execution time and energy but also optimal architecture usage. We...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction...
CGO
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper, we describe a novel execution environment for Java programs that substantially improves execution performance by incorporating both on-line and off-line profile inf...