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» Reducing Design Complexity of the Load Store Queue
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HPCA
2006
IEEE
14 years 8 months ago
Store vectors for scalable memory dependence prediction and scheduling
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
Samantika Subramaniam, Gabriel H. Loh
HPCA
2011
IEEE
12 years 11 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
JCIT
2007
63views more  JCIT 2007»
13 years 8 months ago
Optimizing Reaching Definitions Overhead in Queue Processors
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderaze...
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
14 years 5 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
INFOCOM
1992
IEEE
14 years 3 days ago
Design of Virtual Channel Queue in an ATM Broadband Terminal Adaptor
In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect diffe...
H. Jonathan Chao, Donald E. Smith