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NOCS
2008
IEEE
14 years 3 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
KDD
2002
ACM
108views Data Mining» more  KDD 2002»
14 years 9 months ago
Incremental Machine Learning to Reduce Biochemistry Lab Costs in the Search for Drug Discovery
This paper promotes the use of supervised machine learning in laboratory settings where chemists have a large number of samples to test for some property, and are interested in id...
George Forman
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
13 years 13 days ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
ICCD
2005
IEEE
98views Hardware» more  ICCD 2005»
14 years 5 months ago
Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature managem...
Anahita Shayesteh, Eren Kursun, Timothy Sherwood, ...
ITC
2003
IEEE
141views Hardware» more  ITC 2003»
14 years 2 months ago
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
Kartik Mohanram, Nur A. Touba