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» Reducing Power Consumption in Backbone Networks
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126
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ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
16 years 14 days ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
116
Voted
DATE
2005
IEEE
108views Hardware» more  DATE 2005»
15 years 9 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
VLSID
2009
IEEE
99views VLSI» more  VLSID 2009»
16 years 4 months ago
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afz...
138
Voted
WINET
2010
147views more  WINET 2010»
14 years 10 months ago
Energy-efficient protocols for wireless networks with adaptive MIMO capabilities
Transmission power control has been used in wireless networks to improve the channel reuse and/or reduce energy consumption. It has been mainly applied to single-input single-outp...
Mohammad Z. Siam, Marwan Krunz, Shuguang Cui, Alaa...
142
Voted
ICON
2007
IEEE
15 years 10 months ago
An Approximate Analysis of the Balance among Performance, Utilization and Power Estimation of Server Systems by Use of the Batch
- In this paper we analyze the performance, utilization, and power estimation of server systems by both adopting the batch service and adjusting the batch size. In addition to redu...
Ying-Wen Bai, Yung-Sen Cheng, Cheng-Hung Tsai