135 search results - page 12 / 27 » Reducing Power Dissipation in SRAM during Test |
ISVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
TCAD
2002
13 years 7 months ago
2002
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing...
ISQED
2003
IEEE
14 years 28 days ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...