135 search results - page 19 / 27 » Reducing Power Dissipation in SRAM during Test |
ITC
1999
IEEE
13 years 12 months ago
1999
IEEE
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
SAC
2006
ACM
14 years 1 months ago
2006
ACM
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
MICRO
2003
IEEE
14 years 27 days ago
2003
IEEE
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...