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» Reducing Power Dissipation in SRAM during Test
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ISWC
1998
IEEE
13 years 12 months ago
Parasitic Power Harvesting in Shoes
system to date has served all of the needs of wearable computing--light weight, minimum effort, high power generation, convenient power delivery, and good power regulation. We beli...
John Kymissis, Clyde Kendall, Joseph A. Paradiso, ...
GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
14 years 22 days ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
PATMOS
2000
Springer
13 years 11 months ago
Dynamic Memory Design for Low Data-Retention Power
Abstract. The emergence of data-intensive applications in mobile environments has resulted in portable electronic systems with increasingly large dynamic memories. The typical oper...
Joohee Kim, Marios C. Papaefthymiou
TON
2008
124views more  TON 2008»
13 years 7 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown
VTS
2006
IEEE
133views Hardware» more  VTS 2006»
14 years 1 months ago
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
Minsik Cho, David Z. Pan