135 search results - page 4 / 27 » Reducing Power Dissipation in SRAM during Test |
EVOW
1999
Springer
13 years 12 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model a...
ISCA
2010
IEEE
13 years 12 months ago
2010
IEEE
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
ICES
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...