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» Reducing Power in High-Performance Microprocessors
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125
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PPOPP
2003
ACM
15 years 9 months ago
The design and implementation of a parallel array operator for the arbitrary remapping of data
Gather and scatter are data redistribution functions of longstanding importance to high performance computing. In this paper, we present a highly-general array operator with power...
Steven J. Deitz, Bradford L. Chamberlain, Sung-Eun...
117
Voted
DAC
1996
ACM
15 years 7 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
135
Voted
IPPS
2007
IEEE
15 years 10 months ago
Determining the Minimum Energy Consumption using Dynamic Voltage and Frequency Scaling
While improving raw performance is of primary interest to most users of high-performance computers, energy consumption also is a critical concern. Some microprocessors allow volta...
Min Yeol Lim, Vincent W. Freeh
137
Voted
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 10 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
152
Voted
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 9 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood