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CODES
2003
IEEE
14 years 24 days ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
SLIP
2009
ACM
14 years 2 months ago
From 3D circuit technologies and data structures to interconnect prediction
New technologies such as 3D integration are becoming a new force that is keeping Moore’s law in effect in today’s nano era. By adding a third dimension in current 2D circuits...
Robert Fischbach, Jens Lienig, Tilo Meister
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
14 years 1 months ago
Statistical model order reduction for interconnect circuits considering spatial correlations
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai,...
FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
14 years 21 days ago
Design of FPGA interconnect for multilevel metalization
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
Raphael Rubin, André DeHon

Publication
273views
12 years 5 months ago
 Beyond Graphs: A New Synthesis.
Artificial neural networks, electronic circuits, and gene networks are some examples of systems that can be modeled as networks, that is, as collections of interconnected nodes. I...
Mattiussi, Claudio, Dürr, Peter, Marbach, Daniel ...