6 search results - page 1 / 2 » Reducing register ports using delayed write-back queues and ... |
ICS
2003
Tsinghua U.
14 years 4 months ago
2003
Tsinghua U.
In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these pararmeters g...
ISLPED
2005
ACM
14 years 4 months ago
2005
ACM
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
HPCA
2005
IEEE
14 years 11 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
GLVLSI
2005
IEEE
14 years 4 months ago
2005
IEEE
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
PACS
2004
Springer
14 years 4 months ago
2004
Springer
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...