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» Reducing the Costs of Bounded-Exhaustive Testing
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PVLDB
2008
108views more  PVLDB 2008»
13 years 7 months ago
Taming verification hardness: an efficient algorithm for testing subgraph isomorphism
Graphs are widely used to model complicated data semantics in many applications. In this paper, we aim to develop efficient techniques to retrieve graphs, containing a given query...
Haichuan Shang, Ying Zhang, Xuemin Lin, Jeffrey Xu...
ETS
2011
IEEE
212views Hardware» more  ETS 2011»
12 years 7 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DATE
2008
IEEE
77views Hardware» more  DATE 2008»
14 years 2 months ago
Re-Examining the Use of Network-on-Chip as Test Access Mechanism
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
Feng Yuan, Lin Huang, Qiang Xu
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 12 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...