43 search results - page 3 / 9 » Reducing the Energy of Speculative Instruction Schedulers |
ISCA
2002
IEEE
14 years 10 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
PACS
2004
Springer
14 years 23 days ago
2004
Springer
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
MICRO
1992
IEEE
13 years 11 months ago
1992
IEEE
- We present a compilation technique for scheduling parallelism on fine grained asynchronous MIMD systems. The shape scheduling algorithm is introduced that utilizes the flexibilit...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...