221 search results - page 19 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will so...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
We apply Amdahl's Law to multicore chips using symmetric cores, asymmetric cores, and dynamic techniques that allows cores to work together on sequential execution. To Amdahl...