221 search results - page 22 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support da...
NOCS
2008
IEEE
14 years 1 months ago
2008
IEEE
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...