221 search results - page 30 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
LPNMR
2009
Springer
2009
Springer
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
14 years 2 months ago
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects...