221 search results - page 4 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
DSD
2003
IEEE
14 years 1 months ago
2003
IEEE
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
HOTI
2008
IEEE
14 years 3 months ago
2008
IEEE
The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-onchip...
TACO
2010
13 years 7 months ago
2010
3DIC
2009
IEEE
13 years 12 months ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
DAC
2010
ACM
14 years 15 days ago
2010
ACM
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...