1182 search results - page 80 / 237 » Reducing the Overhead of Dynamic Analysis |
107
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DAC
1999
ACM
16 years 4 months ago
1999
ACM
? The economic viability of the reusable core-based design paradigm depends on the development of techniques for intellectual property protection. We introduce the first dynamic wa...
155
Voted
INFOCOM
2011
IEEE
14 years 7 months ago
2011
IEEE
—In a sensor network, an important problem is to provide privacy to the event detecting sensor node and integrity to the data gathered by the node. Compromised source privacy can...
129
Voted
ASPDAC
2004
ACM
15 years 9 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
176
Voted
RTAS
1996
IEEE
15 years 7 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
135
Voted
MICRO
2008
IEEE
15 years 10 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...