Sciweavers

723 search results - page 102 / 145
» Reducing the complexity of the issue logic
Sort
View
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 21 days ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 11 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
ICCD
2008
IEEE
192views Hardware» more  ICCD 2008»
14 years 4 months ago
Energy-aware opcode design
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
ICCAD
2010
IEEE
125views Hardware» more  ICCAD 2010»
13 years 5 months ago
Peak current reduction by simultaneous state replication and re-encoding
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou
ESOP
2004
Springer
14 years 1 months ago
Resources, Concurrency, and Local Reasoning (Abstract)
t) Peter W. O’Hearn Queen Mary, University of London In the 1960s Dijkstra suggested that, in order to limit the complexity of potential process interactions, concurrent programs...
Peter W. O'Hearn