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GECCO
2003
Springer
129views Optimization» more  GECCO 2003»
14 years 16 days ago
Inherent Fault Tolerance in Evolved Sorting Networks
This poster paper summarizes our research on fault tolerance arising as a by-product of the evolutionary computation process. Past research has shown evidence of robustness emergin...
Rob Shepherd, James A. Foster
DATE
2009
IEEE
111views Hardware» more  DATE 2009»
14 years 2 months ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb...
ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
14 years 1 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
GECCO
2008
Springer
186views Optimization» more  GECCO 2008»
13 years 8 months ago
A pareto following variation operator for fast-converging multiobjective evolutionary algorithms
One of the major difficulties when applying Multiobjective Evolutionary Algorithms (MOEA) to real world problems is the large number of objective function evaluations. Approximate...
A. K. M. Khaled Ahsan Talukder, Michael Kirley, Ra...
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
14 years 1 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...