65 search results - page 10 / 13 » Reducing traffic generated by conflict misses in caches |
EUROPAR
2001
Springer
13 years 12 months ago
2001
Springer
In this paper, we present a new hybrid branch predictor called the GoStay2, which can effectively reduce indirect misprediction rates. The GoStay2 has two different mechanisms comp...
ASPLOS
1987
ACM
13 years 11 months ago
1987
ACM
One potentialdisadvantage of a machine with a reduced instruction. set is that object programs may be substantially larger than those for a machine with a richer, more complex ins...
MICRO
2002
IEEE
13 years 7 months ago
2002
IEEE
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...