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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
VTC
2006
IEEE
14 years 3 months ago
Throughput Performance of Iterative Frequency-Domain SIC with 2D MMSE-FDE for SC-MIMO Multiplexing
— Broadband wireless packet access will be the core technology of the next generation mobile communication systems. For very high-speed and high-quality packet transmissions in a...
Akinori Nakajima, Fumiyuki Adachi
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab
COMSWARE
2007
IEEE
14 years 1 months ago
QoS-driven middleware for optimum provisioning of location based services
This paper proposes a middleware to reduce the and consistency are usually poor since they depend on cell consumption of network resources and optimize the provision of size; GPS t...
Israel Martín-Escalona, Francisco Barcel&oa...
EDCC
2006
Springer
14 years 1 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...