73 search results - page 5 / 15 » Reduction of interpolants for logic synthesis |
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
CSREAESA
2006
13 years 9 months ago
2006
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...