73 search results - page 8 / 15 » Reduction of interpolants for logic synthesis |
CODES
2003
IEEE
14 years 27 days ago
2003
IEEE
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) ...
AGP
2010
IEEE
13 years 11 months ago
2010
IEEE
We present an overview of the program transformation techniques which have been proposed over the past twenty-five years in the context of logic programming. We consider the appro...