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DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 2 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy
INFOCOM
2007
IEEE
14 years 1 months ago
Lava: A Reality Check of Network Coding in Peer-to-Peer Live Streaming
—In recent literature, network coding has emerged as a promising information theoretic approach to improve the performance of both peer-to-peer and wireless networks. It has been...
Mea Wang, Baochun Li
SECON
2007
IEEE
14 years 1 months ago
OPERA: An Optimal Progressive Error Recovery Algorithm for Wireless Sensor Networks
—Wireless Sensor Networks (WSNs) require robustness against channel induced errors while retransmission based schemes prove too costly for energy constrained sensor nodes. Channe...
Saad B. Qaisar, Hayder Radha
CGO
2005
IEEE
14 years 1 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
ISCA
2005
IEEE
117views Hardware» more  ISCA 2005»
14 years 1 months ago
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
Amir Roth