10 search results - page 2 / 2 » Redundant wire insertion for yield improvement |
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- Reducing the yield loss due to via failure is one of the important problems in design for manufacturability. A well known and highly recommended method to improve via yield/relia...
ASPDAC
2007
ACM
14 years 16 days ago
2007
ACM
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...