Sciweavers

279 search results - page 19 / 56
» Refined statistical static timing analysis through
Sort
View
ICDCIT
2005
Springer
14 years 3 months ago
Analyzing Loop Paths for Execution Time Estimation
Abstract. Statically estimating the worst case execution time of a program is important for real-time embedded software. This is difficult even in the programming language level du...
Abhik Roychoudhury, Tulika Mitra, Hemendra Singh N...
IEEEPACT
1999
IEEE
14 years 2 months ago
Predicated Static Single Assignment
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
DAC
2008
ACM
14 years 11 months ago
Parameterized timing analysis with general delay models and arbitrary variation sources
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
Khaled R. Heloue, Farid N. Najm
ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
14 years 4 months ago
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
Bao Liu
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
14 years 1 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah