76 search results - page 14 / 16 » Register placement for low power clock network |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock sync...
IWNAS
2008
IEEE
14 years 2 months ago
2008
IEEE
∗ As one type of stealthy and hard-to-detect attack, lowrate TCP-targeted DDoS attack can seriously throttle the throughput of normal TCP flows for a long time without being noti...
NOCS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...