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HPCA
2006
IEEE
14 years 9 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
DAC
1998
ACM
14 years 10 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
DAC
2010
ACM
13 years 9 months ago
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is appli...
Lin Xie, Azadeh Davoodi, Kewal K. Saluja
IPSN
2007
Springer
14 years 3 months ago
Lucid dreaming: reliable analog event detection for energy-constrained applications
— Existing sensor network architectures are based on the assumption that data will be polled. Therefore, they are not adequate for long-term battery-powered use in applications t...
Sasha Jevtic, Mathew Kotowsky, Robert P. Dick, Pet...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 2 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...