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CF
2004
ACM
14 years 2 months ago
Fault tolerant clockless wave pipeline design
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...
DAC
2009
ACM
14 years 10 months ago
Thermal-driven analog placement considering device matching
With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the ther...
Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-...
ISQED
2008
IEEE
66views Hardware» more  ISQED 2008»
14 years 3 months ago
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
– As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was ...
Ming-Fang Lai, Hung-Ming Chen
DAC
2005
ACM
13 years 11 months ago
Response compaction with any number of unknowns using a new LFSR architecture
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
Erik H. Volkerink, Subhasish Mitra
FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
14 years 20 days ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...