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» Reliability-Centric High-Level Synthesis
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ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 11 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
TCAD
2010
121views more  TCAD 2010»
13 years 4 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
14 years 2 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
ISSS
1996
IEEE
94views Hardware» more  ISSS 1996»
14 years 1 months ago
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification
Luca Benini, Patrick Vuillod, Claudionor Jos&eacut...